As semiconductor technology continues to evolve, improvement of IC performance is mainly achieved through shrinking the size of integrated circuit devices to increase their speed. Currently, advances in the semiconductor enable high density, high performance, and low cost manufacturing of electronic devices. However, the feature sizes of nanotechnology are constrained by physical limits.
As CMOS device dimensions continue to shrink, the challenges in manufacturing processes lead to a three-dimensional design, such as the development of fin field effect transistors (FinFETs). In comparison to conventional planar transistors, FinFET technology is used in advanced semiconductor devices having 22 nm nodes and below, which can effectively control the devices as a result of scaling to overcome the short channel effect and improve the transistor density. In a FinFET device, the gate is formed around the fin shaped channel, so that the static electricity can be controlled from three sides for a more prominent performance of electrostatic control.
Conventional techniques of forming a fin shaped channel FinFET device use the following process steps: First, a buried oxide is formed on a silicon layer to produce a silicon on insulator (SOI) structure; next, a second silicon layer is formed on the silicon on insulator structure, the second silicon layer may be monocrystalline or polycrystalline material; the second silicon layer is then patterned by etching to form a fin-shaped channel. Thereafter, a gate structure is formed around the sides and the top surface of the fin-shaped channel, and a stressed silicon-germanium structure is formed at two opposite sides of the fin-shaped channel.
The above-described process of forming a fin-shaped channel uses a <110>, <100> or <111> surface orientation. When a high-k-metal gate process is used to form a high k-metal gate structure disposed on both sides of the fin-shaped channel, the surface roughness of the fin-shaped channel will affect the changes in the metal work function under the gate metal layer, resulting in a decrease in electrical properties of the high k-metal gate structure.